1. Field
Example embodiments relate to layouts of a complementary metal oxide semiconductor (CMOS) inverters. More particularly, example embodiments relate to layouts of CMOS inverters, in which the width of a gate electrode has a minimum feature size, as defined below in this application, and an effective channel length is increased to have a longer delay than conventional inverters.
2. Description of the Related Art
As used herein, the terms “minimum feature size” denote a dimension of the smallest feature actually constructed in a semiconductor manufacturing process. Because chipmakers continually seek to provide more circuitry into the same amount of space, there is a general desire to continue reducing the minimum feature size.
In CMOS technology processes, gate electrodes are generally formed of poly silicon. Of course, gate electrodes are not limited being made of poly silicon. In this disclosure, a gate electrode will be referred to as a “poly” and multiple gate electrodes will be referred to as “polies”. Accordingly, the width of the gate electrode will be referred to as “poly length”. Also, an interval between adjacent polies is referred to herein as a “poly interval”. The terms “poly”, “polies”, “poly length” and “poly interval” as used herein should be understood as being applicable to CMOS circuits having a gate electrode formed of poly silicon as well as a gate electrode formed of materials other than poly silicon.
In CMOS technology processes, if a poly length is about 50 nm, CMOS transistor characteristics tend to be largely influenced by poly intervals. Accordingly, there is a growing desire to reduce a process variation by arranging polies at regular intervals.
Unlike an analog circuit, a digital circuit generally uses a CMOS transistor whose poly length has a minimum feature size. However, some types of digital circuits, such as a hold buffer requiring a long delay, for example, use polies having a length greater than the minimum feature size. To reduce a process variation, poly lengths should be uniform and the polies should be aligned at regular intervals. However, in conventional devices including a first type of circuit requiring a longer and a second type of circuit requiring a shorter delay, difficulties arise when attempting to align the polies of the first type of circuit and the second type of circuit at regular intervals.
FIG. 1 is a circuit diagram representing a conventional inverter 10. Referring to FIG. 1, the conventional inverter 10 includes a PMOS transistor MP1 and an NMOS transistor MN1. The PMOS transistor MP1 is connected between a first line 102 for receiving a first voltage Vdd and an output terminal OUT. The NMOS transistor MN1 is connected between the output terminal OUT and a second line 104 for receiving a second voltage Vss. Further, each gate of a pair of the transistors MP1 and MN1 is connected to an input terminal IN.
FIG. 2 is a diagram illustrating a conventional layout 100 for the inverter 10 of FIG. 1. Referring to FIGS. 1 and 2, the PMOS transistor MP1 is formed in a P active region 101 in an N-well region, and the NMOS transistor MN1 is formed in an N active region 103 in a P-substrate or a P-well region.
A source of the PMOS transistor MP1 is connected to the first line 102 for receiving the first voltage Vdd through a metal line and a via. The drain of the PMOS transistor MP1 is connected to an output terminal OUT and the drain of the NMOS transistor MN1 through a metal line and a via. The source of the NMOS transistor MN1 is connected to the second line 104 for receiving the second voltage Vss through a metal line and a via. Each of the gates of the PMOS transistor MP1 and the NMOS transistor MN1 is connected to the input terminal IN through a poly and via passing through the center of the P active region 101 and the N active region 103.
In the conventional CMOS inverter 10, a channel length may be reduced by setting the poly length to the minimum feature size. Reducing the channel length generally reduces a delay of an output signal.
FIG. 3 is a diagram illustrating another conventional layout 110 of the conventional inverter 10. A comparison of FIG. 2 and FIG. 3 indicates that an inverter 10 having the layout 110 has a longer poly length than an inverter 10 having the layout 100. Further, the active regions and channel widths shown in the layout 110 of FIG. 3 are narrower than the active regions and channel widths shown in the layout 100 of FIG. 2. All other factors being equal, an inverter 10 having the layout 110 of FIG. 3 will have a longer delay than an inverter 10 having the layout 100 because the layout 110 of FIG. 3 has a longer poly length and narrower widths of the active regions and the channels.
Conventionally, if an integrated circuit includes a first type of circuit having an first poly length and a second type of circuit having different poly length, it is difficult, complex and/or expensive to align the polies at regular intervals. For example, if polies having different poly lengths are aligned at regular intervals in an integrated circuit, poly pitch of the integrated circuit is not uniform. In the alternative, if the poly pitch is uniform in an integrated circuit having polies with at least two different poly lengths, the poly intervals are not uniform. In light of the above-identified difficulties, costs, process variations and layout areas for an integrated circuit may increase.